A grounded-gate NMOS (“ggNMOS”) structure is conventionally used as an electrostatic discharge (“ESD”) protection device, such as a clamp for an ESD pulse. In such a conventional structure, a gate, a source region, and a body region of an NMOS transistor are all connected to one another for connecting to ground. Such body region may be associated with a base region of a parasitic lateral NPN transistor of such NMOS transistor, namely a parasitic NPN bipolar junction transistor (“BJT”). A drain region of such NMOS transistor may be coupled to a pad, such as a voltage supply pad or an input/output (“I/O”) pad for example.
In operation, a positive ESD transient with respect to ground appearing at such I/O pad may cause avalanche multiplication generating electron-hole pairs, namely a hole current. Such hole current may flow to such ground from a base region of such BJT across a lateral resistance of a substrate, sometimes referred to as a “parasitic” lateral substrate resistance, to a p+ bulk region or tap in such substrate or p-well (hereinafter collectively and singly “substrate”). This current flowing across such a substrate resistance may cause a voltage to buildup triggering a “snapback” of the p+ tap-to-source junction, which may be used to dissipate energy to ground. Even though the term “bulk region” is used, the description herein applies to both bulk silicon wafers and silicon-on-insulator wafers. Other details regarding a ggNMOS structure may be found in “On-Chip ESD Protection for Integrated Circuits,” by Albert Z. H. Wang, Kluwer Academic Publishers, published in 2002, at pages 54-55.
Generally, ggNMOS “snapback” happens when voltage applied at a pad, such as a voltage supply pad or I/O pad is higher than a trigger voltage. This condition of a voltage at such a pad being higher than a trigger voltage may lead to generation of holes due to impact ionization at a drain junction. A substrate current (e.g., a hole current) may flow through a substrate raising substrate potential. Such increase in substrate potential may eventually cause a source-to-substrate junction to be forward biased. Such forward biased condition may cause a substantial amount of electrons to be injected into such substrate. Such injected electrons may diffuse to a drain region, which in turn may generate excess electron-hole pairs. This generation of excess electron-hole pairs may cause a positive feedback effect which turns on a parasitic NPN BJT. Because such parasitic NPN BJT is turned on, such parasitic NPN BJT can sink a much higher level of current than an avalanche-breakdown current of a drain-to-substrate diode, and thus such parasitic NPN BJT goes into a stable snapback region.
Unfortunately, heretofore ggNMOS snapback used to facilitate substrate pumping (e.g., pumping of substrate current) for ESD consumed significant amounts of semiconductor real estate. Conventionally, ggNMOS structures were constrained to be laid out in a tile formation, where the entire layout had a square or square-like shape with a width (W) to length (L) ratio (W/L) equal to or at least approximately equal to 1. In such a layout, p+ taps were placed at the outer perimeter or edge of such a “square” to provide a sufficiently large substrate resistance. This layout constraint has meant a significant amount of semiconductor real estate is consumed for providing such separation to provide for a sufficiently large substrate resistance.
Hence, it is desirable and useful to provide a semiconductor structure for an ESD protection device for an IC that overcomes one or more of the above-described limitations.